Its output drives a 4027 J-K flipflop, which divides the oscillator signal in half to ensure an equal mark/space ratio. Two elements of a 4066 quad bilateral switch (IC3c & IC3d) are alternately switched on by the complementary outputs of the J-K flipflop. One switch input (pin 11) is connected to +5V, whereas the other (pin 8) is connected to -5V. The outputs (pins 9 & 10) of these two switches are connected together, with the result being a ±5V 100kHz square wave. Series resistance is included to current-limit the signal before it is applied to the capacitor under test via a pair of test probes. Diodes D1 and D2 limit the signal swing and protect the 4066 outputs in case the capacitor is charged.
Next, momentarily short the test probes together and adjust VR4 for 0mV at pin 6 of IC4. That done, set your meter to read milliamps and connect it between TP4 and the negative (-) DMM output. Apply -5V to TP2 and note the current flow, which should be around 2.1mA. Transfer the -5V from TP2 to TP1 and adjust VR2 until the same current (ignore sign) is obtained. Remove the -5V from TP1. Again, set to your meter to read volts and connect it to the DMM outputs. Apply the probes to a 10W resistor and adjust VR3 for a reading of 100mV. Finally, ensure that all capacitors to be tested are always fully discharged before connecting the probes.
Author: Len Cox - Copyright: Silicon Chip Electronics